JPH0314805U - - Google Patents

Info

Publication number
JPH0314805U
JPH0314805U JP7447489U JP7447489U JPH0314805U JP H0314805 U JPH0314805 U JP H0314805U JP 7447489 U JP7447489 U JP 7447489U JP 7447489 U JP7447489 U JP 7447489U JP H0314805 U JPH0314805 U JP H0314805U
Authority
JP
Japan
Prior art keywords
integrated circuit
carrier
monolithic integrated
view
perspective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7447489U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7447489U priority Critical patent/JPH0314805U/ja
Publication of JPH0314805U publication Critical patent/JPH0314805U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mounting Of Printed Circuit Boards And The Like (AREA)
  • Die Bonding (AREA)
  • Waveguides (AREA)
JP7447489U 1989-06-26 1989-06-26 Pending JPH0314805U (en])

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7447489U JPH0314805U (en]) 1989-06-26 1989-06-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7447489U JPH0314805U (en]) 1989-06-26 1989-06-26

Publications (1)

Publication Number Publication Date
JPH0314805U true JPH0314805U (en]) 1991-02-14

Family

ID=31614192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7447489U Pending JPH0314805U (en]) 1989-06-26 1989-06-26

Country Status (1)

Country Link
JP (1) JPH0314805U (en])

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